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| 74ABT273 Octal D-Type Flip-Flop January 1993 Revised March 2005 74ABT273 Octal D-Type Flip-Flop General Description The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Features s Eight edge-triggered D-type flip-flops s Buffered common clock s Buffered, asynchronous Master Reset s See ABT377 for clock enable version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Disable time less than enable time to avoid bus contention Ordering Code: Order Number 74ABT273CSC 74ABT273CSJ 74ABT273CMSA 74ABT273CMTC 74ABT273CMTCX_NL (Note 1) Package Number M20B M20D MSA20 MTC20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Connection Diagram Pin Descriptions Pin Names D0-D7 MR CP Q0-Q7 Data Inputs Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Outputs Description (c) 2005 Fairchild Semiconductor Corporation DS011549 www.fairchildsemi.com 74ABT273 Truth Table Operating Mode MR Reset (Clear) Load "1" Load "0" L H H Inputs CP Dn X h l Output Qn L H L X H HIGH Voltage Level steady state h HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L LOW Voltage Level steady state I LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X Immaterial LOW-to-HIGH clock transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74ABT273 Absolute Maximum Ratings(Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current (Across Comm Operating Range) Over Voltage Latchup VCC 4.5V twice the rated IOL (mA) 65qC to 150qC 55qC to 125qC 55qC to 150qC 0.5V to 7.0V 0.5V to 7.0V 30 mA to 5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate ('V/'t) Data Input Enable Input 50 mV/ns 20 mV/ns 40qC to 85qC 4.5V to 5.5V 0.5V to 4.75V 0.5V to VCC Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. 500 mA DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOS ICEX ICCH ICCL ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Short-Circuit Current Output HIGH Leakage Current Power Supply Current Power Supply Current Maximum ICC/Input Outputs Enabled 4.75 2.5 2.0 0.55 1 1 7 Min 2.0 0.8 Typ Max Units V V V V V Min Min Min Max Max VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN IOH IOH IOL VIN VIN VIN VIN VIN IID 1.2 18 mA 3 mA 32 mA 64 mA 2.7V (Note 4) VCC 7.0V 0.5V (Note 4) 0.0V 1.9 PA 0.0V VCC PA PA 1 1 PA V Max 0.0 Max Max Max Max Max All Other Pins Grounded 100 275 50 50 30 1.5 mA VOUT VOUT PA PA mA mA All Outputs HIGH All Outputs LOW VI VCC 2.1V VCC 2.1V Data Input VI All Others at VCC or GND ICCD Dynamic ICC No Load 0.3 mA/ MHz Note 4: Guaranteed but not tested. Note 5: For 8 bits toggling, ICCD 0.5 mA/MHz. Max Outputs Open (Note 5) One Bit Toggling, 50% Duty Cycle 3 www.fairchildsemi.com 74ABT273 AC Electrical Characteristics (SSOIC package) TA Symbol Parameter Min fMAX tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay CP to On Propagation Delay MR to On 150 2.0 2.8 2.5 VCC CL 25qC 5.0V 50 pF Typ 200 6.0 6.8 7.4 Max TA 55qC to 125qC 4.5V to 5.5V 50 pF Max 7.0 7.5 8.2 CL Min 150 1.0 1.0 1.0 TA VCC 40qC to 85qC 4.5V to 5.5V CL 50 pF Max MHz 6.0 6.8 7.4 ns ns Units VCC Min 150 2.0 2.8 2.5 AC Operating Requirements TA Symbol Parameter VCC CL Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Pulse Width, CP, HIGH or LOW Master Reset Pulse Width, LOW Recovery Time MR to CP 2.0 2.5 1.2 1.2 3.3 3.3 3.3 2.0 25qC 5.0V 50 pF Max TA 55qC to 125qC 4.5V to 5.5V 50 pF Max CL Min 2.0 2.5 1.4 1.4 3.3 3.3 3.3 2.0 TA VCC 40qC to 85qC 4.5V to 5.5V 50 pF Max ns ns ns ns ns Units CL VCC Min 2.0 2.5 1.2 1.2 3.3 3.3 3.3 2.0 Capacitance (SOIC package) Symbol CIN COUT (Note 6) Parameter Input Capacitance Output Capacitance Typ 5 9 1 MHz, per MIL-STD-833, Method 3012. Units pF pF VCC VCC 0V 5.0V Conditions TA 25qC Note 6: COUT is measured at frequency f www.fairchildsemi.com 4 74ABT273 AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. VM 1.5V Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 6. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 4. Propagation Delay, Pulse Width Waveforms FIGURE 5. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.fairchildsemi.com 74ABT273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 74ABT273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74ABT273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 www.fairchildsemi.com 8 74ABT273 Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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